The present invention relates to a nonvolatile semiconductor memory device capable of erasing and writing data after changing condition from standby to operation.
A so-called UV-EPROM is an ultraviolet-erasable and programmable read only memory in which data are erased by an irradiation of ultraviolet rays and electrically written again. A so-called EEPROM is an electrically erasable and programmable read only memory in which data are electrically erased and written. In such the UV-EPROM and EEPROM, data of "1" or "0" are read out on the basis of a determination result of comparing a read potential V.sub.S (called as V.sub.S1 or V.sub.S0 corresponding to the necessity) corresponding a level of "1" or "0" of cell data with a reference potential (called as V.sub.R) in a sense amplifier circuit when the data are read out.
FIG. 1A is a plan view showing a pattern of a nonvolatile transistor which is used as memory cell in the EEPROM electrically erasing data, and FIG. 1B is a sectional view showing a section cut by a line 1B--1B in FIG. 1A.
The transistor has a double poly-crystal silicon layer construction, in which a floating gate 21 is formed by a first poly-crystal silicon layer and a control gate 23 is constituted by a second poly-crystal silicon layer. In FIGS. 1A and 1B, numeral 24 denotes a source, 25 denotes a drain, 27 denotes a silicon substrate, 22 denotes a contact hole, and 28 denotes a data line which is formed by aluminum (Al) and connected through the contact hole 22 to the drain 25. There will be briefly described below data writing, reading and erasing operation of the memory cell having the above construction.
Writing operation is performed by implanting a hot electron into the floating gate under the condition that a drain potential is set to 8 V, the control gate potential is 12 V and a source voltage is 0 V. Reading operation is performed under the condition that the control gate potential is set to 5 V, the drain potential is 1 V and the source potential is 0 V. At this time, very few cell current flows between the source and drain when storage data of the memory cell is "0" (a write mode), and a cell current having about 100 .mu.A flows between the source and drain when the storage data is "1" (an erasing mode).
Erasing operation is performed under the condition that the control gate potential is 0 V, the drain potential is floating and the source potential is high such as 12 V. At this time, an electron in the floating gate is extracted to the source by means of a tunnel effect.
There is described a total configuration of the conventional nonvolatile semiconductor memory device including the above-mentioned nonvolatile memory cell and sense amplifier with reference to FIG. 2. In FIG. 2, the memory device comprises a memory cell array 1 in which a plurality of memory cells are arranged in a matrix shape, a dummy cell array 3 comprised of a dummy cell having the same construction as the plurality of memory cells along a line in the column direction of the memory cell array 1, a read potential generation circuit 6 for supplying a predetermined potential a memory cell selected at reading data and for generating a read potential corresponding to a cell current in the memory cell selected, a reference potential generation circuit 8 for supplying a predetermined drain potential to a drain of the dummy cell selected at reading data and for generating a reference potential at reading data, an equalizing circuit 7 for equalizing corresponding nodes in the read and reference potential generation circuits 6 and 8, and a current mirror type amplifier circuit 10 for comparing the read potential and the reference potential respectively supplied from the read and reference potentials generation circuits 6 and 8 and for transmitting a potential corresponding to the data of the selected memory cell to an output circuit (not shown in FIG. 2).
The read potential generation circuit 6, the equalizing circuit 7, the reference potential generation circuit 8 and current mirror type amplifier circuit 10 constitute the conventional sense amplifier which is materially configured in FIG. 3, for example.
In FIG. 3, numerals P1-P23 denote P-channel enhancement transistors, D1-D12 denote N-channel depression transistors, N1-N24 denote N-channel enhancement transistors, and I1-I12 denote N-channel transistors each having a threshold value near 0 volt (V). In FIG. 3, the read potential generation circuit 6 comprises the transistors P1, D1 and I1 which are connected in series one another, the transistor N1, the transistors P2, D2 and I2 which are connected in series one another, the transistors N2, N3, N4, N5, N6, N7 and N8, and the transistors P3 and P4 which are connected in series each other. A driving voltage V.sub.CC is supplied to sources of the transistors P1, P2 and P3, and sources of the transistors N1, N2, N4, N6, N8, I1 and I2 are grounded to the earth. A gate of the transistor D1 is connected to a junction point between the transistors D1 and I1. A drain of the transistor N1 is connected to a junction point between the transistors D1 and I1. A gate of the transistor D2 is connected to a junction point between D2 and I2. A drain of the transistor N2 is connected to a junction point between the transistors D2 and I2. A driving voltage V.sub.CC is supplied to a drain of the transistor N3 of which a gate is connected to the junction point between the transistors D1 and I1 and a source is connected to a node ND.sub.1. A drain of the transistor N4 is connected to the node ND.sub.1 and issues a minute current (for example, about 1 .mu.A) by a leak control signal S.sub.CL supplied to a gate thereof in order to prevent a data line from an overcharge when data "0" are read out for a long time. The transistor N5 has a drain connected to the node ND.sub.1 and a source connected to one end of a transfer gate provided between the read potential generation circuit 6 and the memory cell array 1, and is turned on only when the data are read. A drain of the transistor N6 is connected to the node ND.sub.1, and a drain of the transistor N8 is connected to a node ND.sub.2. The node ND.sub.2 is connected to the node ND.sub.1 through the transistor N7. A driving voltage V.sub.CC is supplied a source of the transistor P3, and gate and drain of the transistor P4 are connected to the node ND.sub.2. Each gate of the transistors P1, P2, P3, N1, N2, N6 and N8 is supplied with a first control signal S.sub.1 which becomes an "L" at reading data. Furthermore, a third control signal *S.sub.3 is supplied to a gate of the transistor N5.
In the read potential generation circuit 6, a series circuit of the transistors P1, D1 and I1, a series circuit of the transistors P2, D2 and I2, and the transistors N3 and N7 keep drain potentials of the memory cells to a optimum value such as 1 V, and transmit a read potential V.sub.S corresponding to the data of the selected memory cell from the node ND.sub.2 to the current mirror amplifier circuit 10. The transistor P4 supplies a constant current as a load transistor of the node ND.sub.2.
Here, the read potential is described. When the data of the memory cell selected from the memory cell array 1 are "0" level, no current flows in the memory cell, and a potential such as 3 V is charged in the node ND.sub.2 through the transistors P3 and P4. When the data of the memory cell selected are "1" level, since a cell current such as 100 .mu.A flows in the memory cell, a potential V.sub.SA1 of the node ND.sub.2 becomes about 1 V, for example, in accordance with a voltage divided ratio between the load transistor P4 and the selected memory cell.
On the other hand, the reference potential generation circuit 8 is a copy circuit of the read potential generation circuit 6, and comprises transistors P11, D11 and I11 connected in series one another, transistors P12, D12 and I12 connected in series one another, transistors N12, N13, N14, N15, N16, N17 and N18, and transistors P13 and P14 connected in series each other. Namely, the transistor P11 of the reference potential generation circuit 8 corresponds to the transistor P1 of the read potential generation circuit 6. A gate of the transistor N15 is supplied with a fourth control signal *S.sub.4.
The reference potential generation circuit 8 is connected through the transistor N15 and a dummy data line DL.sub.R to the dummy cell 3, and the transistors P11, D11, I11, P12, D12, I12, N13 and N17 keep a drain potential of the dummy cell 3 to a predetermined potential. The transistor P14 supplies a constant current having a reference potential V.sub.R. A node ND.sub.4 issuing the reference potential is connected to the dummy data line DL.sub.R through the transistors N17 and N15. Since dummy cells DC1-DCm are the cells in erasing mode, a cell current of 100 .mu.A flows at reading the data. The reference potential V.sub.R at this time becomes a value being a current ratio between the load transistor P14 and the selected dummy cell. on the other hand, the reference potential V.sub.R needs to be an intermediate potential between the read potential V.sub.S when the data "0" are stored in the memory cell CAij and the read potential V.sub.S when the data "1" is stored. Accordingly, the load transistor P14 of the reference potential generation circuit 8 has a predetermined current amount more than that of the corresponding transistor P4 of the read potential generation circuit 6.
The current mirror type amplifier circuit 10 has a differential amplifier pair including transistors P21, P22, P23, N22 and N23, a transistor N24, and inverters IV1, IV2 and IV3. A gate of the transistor P23 is connected to the node ND.sub.2 issuing the read potential V.sub.S, and a gate of the transistor P23 is connected to the node ND.sub.4 issuing the reference potential V.sub.R. A drain of the transistor N24 is connected to drains of the transistors P22 and N22, and a source of the transistor N24 is grounded to the earth. The inverters IV1, IV2 and IV3 are connected in series one another, and inverts a potential of a junction point between the transistors P22 and N22 to output it to an output circuit. Accordingly, the read potential V.sub.S and the reference potential V.sub.R are supplied to the transistors P22 and P23, respectively, and an output D.sub.B is supplied to the output circuit 12 according to an amount of these values. The output D.sub.B becomes "1" when the data "0" are read, and does "0" when the data "1" are read.
The nodes ND.sub.1 and ND.sub.3 are connected by the transistor N20, the nodes ND.sub.2 and ND.sub.4 are connected by the transfer gate comprised of the transistors P20 and N21, and these transistors N20, P20 and N21 constitute the equalizing circuit 7. The equalizing circuit 7 comprises the transistor N20 for equalizing the nodes ND.sub.1 and ND.sub.3, and the transistors N21 and P20 for equalizing the nodes ND.sub.2 and ND.sub.4.
In the semiconductor memory device having the above configuration, during a standby where the data are not read, the first control signal S.sub.1 being "H" during the standby is supplied to gates of the transistors N1. N2, N6, and N8 of the read potential generation circuit 6 and gates of the transistors N11, N12, N16, and N18 of the reference potential generation circuit 8 in order to suppress a power consumption, so that all nodes ND.sub.1, ND.sub.2, ND.sub.3 and ND.sub.4 are grounded to the earth. At this time, an inverted signal *S.sub.2, which is generated by inversion of the second control signal supplied to the gates of the transistors P21 and N24 of the current mirror circuit 10 and the gates of the transistors n20 and N21, is "H" level, and the second control signal supplied to the gate of the transistor P20 is "L" level.
In the case that there is a condition changed from a standby mode to a reading mode, changes of several signals *CE, S.sub.1, WL, *S.sub.2,D.sub.0, V.sub.S and V.sub.R are shown in FIG. 4. In FIG. 4, a change of a first control signal S.sub.1 from "H" to "L" by receiving a chip enable signal *CE causes the read potential generation circuit 6 and reference potential generation circuit 8 to be an operation mode, thereby outputting data D.sub.0 from the current mirror amplifier circuit 10 to a not-shown output circuit. Since a potential WL of a word line needs an enough time to be risen by means of a capacity of the memory cells, it is impossible to normally read the data during a rising time interval. On the other hand, since a current flows in a data line by charging a drain potential of the transistor P4 despite of data the memory cell, a level of the read potential V.sub.S is low. In the same manner, the dummy data line DL.sub.R is initially charged. Since the current amount of the transistor P4 is smaller than that of the transistor P14, a charge on the side of the memory cells needs a longer time than a charge on the side of the reference potential. In order to shorten a charge time on the memory cell side, when a predetermined time passes after the control signal S.sub.1 changes from "H" to "L" , the signal *S.sub.2 changes from "H" to "L" and the signal S.sub.2 changes from "L" to "H", thereby equalizing both levels between the nodes ND.sub.2 and ND.sub.4 and between nodes ND.sub.1 and ND.sub.3, respectively, so as to quicken the initial charge. After that, when the signal *S.sub.2 changes from "L" to "H", the current mirror amplifier circuit 10 is driven, thereby PG,10 achieving a high speed reading with respect to stored data by outputting cell data.
In the conventional nonvolatile semiconductor memory device having the above construction, in the case of reading the data "0" when the chip enable signal *CE changes from "H" to "L", if the signals S.sub.2 and *S.sub.2 change during a time period insufficient to initially charge a potential to the data line, the levels of the reference potential V.sub.S and the reference potential V.sub.R are respectively inverted (during times t.sub.1 and t.sub.2 in FIG. 4). Therefore, operation changes from "1" reading to "0" reading, thereby resulting a problem of the delay of reading the data.
Furthermore, in order to quicken the initial reading, the node ND.sub.2 of the read potential generation circuit 6 is equalized to the node ND.sub.4 of the reference potential generation circuit 8. Therefore, when there are provided a plurality of the reference potential generation circuits 6, it is necessary to provide a same number of the reference potential generation circuits 8 and dummy cell arrays 3, thereby resulting a problem of increasing an area of chips.